preliminary information june 2000 copyright ?2000 alliance semiconductor. all rights reserved. ? AS6UA25617 7/14/00 alliance semiconductor 1 1.65v to 3.6v 256k16 inte lliwatt? low power cmos sram with two chip enables features ? AS6UA25617 ? intelliwatt? active power circuitry ? industrial and commercial temperature ranges available ? organization: 262,144 words 16 bits ? 2.7v to 3.6v at 55 ns ? 2.3v to 2.7v at 70 ns ? 1.65v to 2.3v at 100 ns ?cs1 and cs2 for chip selection ? low power consumption: active - 144 mw at 3.6v and 55 ns - 68 mw at 2.7v and 70 ns - 28 mw at 2.3 v and 100 ns ? low power consumption: standby - 72 w max at 3.6v - 41 m w max at 2.7v - 28 m w max at 2.3v ? 1.2v data retention ? equal access and cycle times ? easy memory expansion with cs1 , cs2, oe inputs ? smallest footprint package - 400-mil 44-pin tsop ii - 48-ball fbga ? esd protection 3 2000 volts ? latch-up current 3 200 ma logic block diagram 1024 256 16 array (4,194,304) oe cs1 we column decoder row decoder a0 a1 a2 a3 a4 a6 a7 a8 v dd v ss a12 a5 a9 a10 a11 a14 a15 a16 a17 a13 control circuit i/o1Ci/o8 i/o9Ci/o16 ub lb i/o buffer cs2 pin arrangement (top view) selection guide product v cc range speed (ns) power dissipation min (v) typ 2 (v) max (v) operating (i cc1 )standby (i sb2 ) max (ma) max ( m a) AS6UA25617 2.7 3.0 3.6 55 2 20 AS6UA25617 2.3 2.5 2.7 70 1 15 AS6UA25617 * * advance information. 1.65 2.0 2.3 100 1 12 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 i/o14 i/o 13 v ss v cc i/o12 i/o11 i/o10 i/o9 cs2 a14 a13 a12 a11 a10 a4 cs1 i/o1 i/o 2 i/o3 i/o4 v cc v ss i/o5 i/o6 i/o7 i/o8 we a5 a6 a7 400-pin 400-mil tsop ii 21 22 a8 a9 ub lb i/o16 i/o15 2 a1 3 a2 4 a3 1 a0 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 43 42 41 44 a16 a15 oe a17 48-csp ball-grid-array package 123456 alb oe a 0 a 1 a 2 cs2 bi/o 9 ub a 3 a 4 cs1 i/o 1 ci/o 10 i/o 11 a 5 a 6 i/o 2 i/o 3 dv ss i/o 12 a 17 a 7 i/o 4 v cc ev cc i/o 13 nc a 16 i/o 5 v ss fi/o 15 i/o 14 a 14 a 15 i/o 6 i/o 7 gi/o 16 nc a 12 a 13 we i/o 8 hnca 8 a 9 a 10 a 11 nc
? 2 alliance semiconductor 7/14/00 AS6UA25617 functional description the AS6UA25617 is a low-power cmos 4,194,304-bit static random access memory (sram) device organized as 262,144 words 16 bits. it is designed for memory applications where slow data access, low power, and simple interfacing are desired. equal address access and cycle times (t aa , t rc , t wc ) of 55/70/100 ns are ideal for low-power applications. active high and low chip selects (cs1 and cs2) permit easy memory expansion with multiple-bank memory systems. when cs1 is high, or ub and lb are high or cs2 is low, the device enters standby mode: the AS6UA25617 is guarant eed not to exceed 72 m w power consumption at 3.6v and 55 ns; 41 m w at 2.7v and 70 ns; or 28 m w at 2.3v and 100 ns. the device also returns data when v cc is reduced to 1.5v for even lower power consumption. a write cycle is accomplished by asserting write enable (we ) and chip select (cs1 ) low, ub and/or lb low, and cs2 high. data on the input pins i/o1Ci/o16 is written on the rising edge of we (write cycle 1) or cs1 , cs2 (write cycle 2). to avoid bus contention, external devices should drive i/o pins only after outputs have been disabled with output enable (oe ) or write enable (we ). a read cycle is accomplished by asserting output enable (oe ), chip select (cs1 ) low, ub and/or lb low, with write enable (we ) and cs2 high. the chip drives i/o pins with the data word referenced by the input address. when either chip select or output enable is inactive, or write enable is active, or (ub ) and (lb ), output drivers stay in high-impedance mode. this device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. lb controls the lower bits, i/o1Ci/o8, and ub controls the higher bits, i/o9Ci/o16. all chip inputs and outputs are cmos-compatible, and operation is from either a single 1.65v to 3.6v supply. the device is available in the jedec standard 48-ball fbga and 44-pin tsopii packages. absolute maximum ratings note: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specificat i on is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. truth table key: x = dont care, l = low, h = high. parameter device symbol min max unit volt ag e o n v cc relative to v ss v tin C0.5 v cc + 0.5 v voltage on any i/o pin relative to gnd v ti/o C0.5 v power dissipation p d C1.0w storage temperature (plastic) t stg C65 +150 c temperature with v cc applied t bias C55 +125 c dc output current (low) i out C20ma cs1 cs2 oe we lb ub i/o1C8 i/o9C16 mode power h x x x x x high-z high-z deselected standby x l x x x x high-z high-z deselected standby x x x x h h high-z high-z deselected standby l h h h l x high-z high-z output disabled active l h h h x l high-z high-z output disabled active lhlhlhd out high-z lower byte read active lhlhhlhigh-zd out upper byte read active lhlhl ld out d out wo r d r e a d a c t i ve lhxl lh d in high-z lower byte write active lhxlhlhigh-z d in upper byte write active lhxlll d in d in word write active
? AS6UA25617 7/14/00 alliance semiconductor 3 recommended operating condition (over the operating range) capacitance (f = 1 mhz, t a = room temperature, v cc = nominal)2 parameter description test conditions min max unit v oh output high voltage i oh = 2.1ma v cc = 2.7v 2.4 v i oh = 1.5ma v cc = 2.3v 2.0 i oh = 1.65ma v cc = 1.65v 1.5 v ol output low voltage i ol = 2.1ma v cc = 2.7v 0.4 v i ol = 0.5ma v cc = 2.3v 0.4 i ol = 0.1ma v cc = 1.65v 0.2 v ih input high voltage v cc = 2.7v 2.2 v cc + 0.5 v v cc = 2.3v 2.0 v cc + 0.3 v cc = 1.65v 1.4 v cc + 0.3 v il input low voltage v cc = 2.7v C0.5 0.8 v v cc = 2.3v C0.3 0.6 v cc = 1.65v C0.3 0.4 i ix input load current gnd < v in < v cc C1 +1 m a i oz output load current gnd < v o < v cc ; outputs high z C1 +1 m a i cc v cc operating supply current cs1 = v il , v in = v il or v ih , i out = 0ma, f = 0 v cc = 3.6v 2 ma v cc = 2.7v 1 v cc = 2.3v 1 i cc1 @ 1mhz average v cc operating supply current at 1 mhz cs1 0.2v, v in 0.2v or v in 3 v cc C 0.2v, f = 1ms v cc = 3.6v 2 ma v cc = 2.7v 1 v cc = 2.3v 1 i cc2 average v cc operating supply current cs1 v il , v in = v il , or v ih , f = f max v cc = 3.6v (55/70/100 ns) 40/30/20 ma v cc = 2.7v (55/70/100 ns) 30/25/15 v cc = 2.3v (55/70/100 ns) 25/20/12 i sb cs1 , cs2 power down current; ttl inputs cs1 3 v ih , cs2 = v ih , or ub = lb 3 v ih , other inputs = v il or v ih , f = 0 v cc = 3.6v 100 m a v cc = 2.7v v cc = 2.3v i sb1 cs1 , cs2 power down current; cmos inputs cs1 > v cc C 0.2v, cs2 = + 0.2v, or ub = lb > v cc C 0.2v, other input = 0v C v cc , f = f max v cc = 3.6v 20 m a v cc = 2.7v 15 v cc = 2.3v 12 i sbdr data retention cs1 > v cc C 0.1v, cs2 < + 0.1v, or ub = lb = v cc C 0.1v, f = 0 v cc = 1.2v 2 m a parameter symbol signals test conditions max unit input capacitance c in a, cs1 , cs2, we , oe , lb , ub v in = 0v 5 pf i/o capacitance c i/o i/o v in = v out = 0v 7 pf
? 4 alliance semiconductor 7/14/00 AS6UA25617 read cycle (over the operating range) 3,9 shaded areas indicate preliminary information. key to switching waveforms read waveform 1 (address controlled) 3,6,7,9 read waveform 2 (chip selects, oe , ub , lb controlled) 3,6,8,9 parameter symbol C55 C70 C100 unit notes min max min max min max read cycle time t rc 55 C 70 C 100 C ns address access time t aa C 55 C 70 C 100 ns 3 chip selects access time t acs1,2 C 55 C 70 C 100 ns 3 output enable (oe ) access time t oe C25C35C50ns output hold from address change t oh 10 C 10 C 15 C ns 5 chip selects low to output in low z t clz 10 C 10 C 10 C ns 4, 5 chip selects high to output in high z t chz 020020020ns4, 5 oe low to output in low z t olz 5 C 5 C 5 C ns 4, 5 ub /lb access time t ba C 55 C 70 C 100 ns ub /lb low to low z t blz 10 C 10 C 10 C ns 4, 5 ub /lb high to high z t bhz 020020020ns4, 5 oe high to output in high z t ohz 020020020ns4, 5 power up time t pu 0 C 0 C 0 C ns 4, 5 power down time t pd C 55 C 70 C 100 ns 4, 5 undefined/dont care falling input rising input t oh t aa t rc t oh d out address data valid previous data valid cs1 data valid t rc t aa t blz t ba t bhz address oe cs2 lb , ub d out t olz t oe t oh t olz t oe t oh t acs1 t ohz t ohz t lz t lz t ohz t ohz t hz t hz t acs1
? AS6UA25617 7/14/00 alliance semiconductor 5 write cycle (over the operating range) 11 shaded areas indicate preliminary information. write waveform 1 (we controlled) 10,11 write waveform 2 (chip selects controlled) 10,11 parameter symbol C55 C70 C100 unit notes min max min max min max write cycle time t wc 55 C 70 C 100 C ns chip selects to write end t cw 40 C 60 C 80 C ns 12 address setup to write end t aw 40 C 60 C 80 C ns address setup time t as 0C0C0Cns12 write pulse width t wp 35 C 55 C 70 C ns address hold from end of write t ah 0C0C0Cns data valid to write end t dw 25 C 30 C 40 C ns data hold time t dh 0C0C0Cns4, 5 write enable to output in high z t wz 020020020ns4, 5 output active from write end t ow 5C5C5Cns4, 5 ub /lb low to end of write t bw 35 C 55 C 70 C ns address cs1 lb , ub we d in d out t wc t cw t bw t aw t wp t dw t dh t ow t wz t ah data undefined high z data valid cs2 t cw t ah t as address cs1 lb , ub we d in t wc t bw t wp t dw t dh t ow t wz d out data undefined high z high z data valid t clz cs2 t cw t ah t as t aw t cw t ah t as t aw
? 6 alliance semiconductor 7/14/00 AS6UA25617 data retention characteristics (over the operating range) 13,5 data retention waveform ac test loads and waveforms notes 1during v cc power-up, a pull-up resistor to v cc on cs1 is required to meet i sb specification. 2 this parameter is sampled, but not 100% tested. 3 for test conditions, see ac test conditions . 4t clz and t chz are specified with c l = 5pf as in figure c. transition is measured 500 mv from steady-state voltage. 5 this parameter is guaranteed, but not tested. 6we is high for read cycle. 7cs1 and oe are low and cs2 is high for read cy cle. 8 address valid prior to or coincident with cs1 transition low and cs2 high. 9 all read cycle timings are referenced from the last valid address to the first transitioning address. 10 cs1 or we must be high or cs2 low during address transitions. either cs1 or we asserting high terminates a write cycle. 11 all write cycle timings are referenced from the last valid address to the first transitioning address. 12 ce1 and ce2 have identical timing. 13 1.2v data retention applies to commercial and industrial temperature range operations. 14 c = 30pf, except at high z and low z parameters, where c = 5pf. parameter sym test conditions min max unit vcc for data retention v dr v cc = 1.2v cs1 3 v cc C 0.1v or ub = lb > v cc C 0.1v v in 3 v cc C 0.1v or v in 0.1v 1.2v 3.6 v data retention current i ccdr C2ma chip deselect to data retention time t cdr 0Cns operation recovery time t r t rc Cns parameters 3.0v 2.5v 2.0v unit r1 1105 16670 15294 ohms r2 1550 15380 11300 ohms r th 645 8000 6500 ohms v th 1.75v 1.2v 0.85v volts v cc cs1 t r t cdr data retention mode v cc v cc v dr 3 1.2v v ih v ih v dr cs2 t r t cdr v ih v ih v dr v cc r1 r2 output 30 pf including jig and scope (a) v cc r1 r2 output 5 pf all input pulses (b) 10% 90% 10% 90% gnd v cc typ < 5 ns (c) thevenin equivalent: output r th v including jig and scope
? AS6UA25617 7/14/00 alliance semiconductor 7 typical dc and ac characteristics package diagrams and dimensions supply voltage (v) 1.7 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i cc normalized supply current supply voltage (v) 0.0 0.25 0.5 0.75 1.0 normalized t aa normalized access time vs. supply voltage vs. supply voltage ambient temperature ( c) C55 105 25 0.5 1.0 0.0 1.5 2.0 2.5 normalized i sb2 normalized standby current vs. ambient temperature v cc = v cc typ supply voltage (v) 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i sb normalized standby current vs. supply voltage i sb2 supply voltage (v) 0.10 0.50 1.0 1.5 normalized i cc normalized i cc vs. cycle time 2.2 2.7 3.2 3.7 1.7 2.2 2.7 3.2 3.7 ta = 25 c 3.0 C0.5 v in = v cc typ 1 5 10 15 11.9 2.8 3.7 v in = v cc typ t a = 25 c v in = v cc typ t a = 25 c v in = v cc typ t a = 25 c a 2 44-pin tsop ii min (mm) max (mm) a1.2 a 1 0.05 a 2 0.95 1.05 b 0.25 0.45 c 0.15 (typical) d 20.85 21.05 e 10.06 10.26 h e 11.56 11.96 e 0.80 (typical) l 0.40 0.60 d h e 1234567891011121314 4443424140393837363534333231 1516 3029 17181920 28272625 c l a 1 e 44-pin tsop ii 0C5 21 24 22 23 e a b
? 8 alliance semiconductor 7/14/00 AS6UA25617 minimum typical maximum a C 0.75 C b 6.90 7.00 7.10 b1 C 3.75 C c 10.90 11.00 11.10 c1 C 5.25 C d 0.30 0.35 0.40 eCC1.20 e1 C 0.68 C e2 0.22 0.25 0.27 yCC0.08 notes 1. bump counts: 48 (8 row 6 column). 2. pitch: (x,y) = 0.75 mm 0.75 mm (typ). 3. units: millimeters. 4. all tolerances are 0.050 unless otherwise specified. 5. typ: typical. 6. y is coplanarity: 0.08 (max). 48-ball fbga top view ball #a1 index bottom view ball #a1 c1 a 1 2 3 4 5 6 a b c d e f g h a b1 c sram die b elastomer detail view side view a y 0.3/typ e2 e die die e e2 e1 d
copyright ?2000 alliance semiconductor corporation (alliance)'s three-point logo, our name, and intelliwatt? are trademarks or r egistered trademarks of alliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make changes to this web site and its products at any time without notice. alliance assumes no responsibility for any errors that may appear in this web site . alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to fitness ? AS6UA25617 7/14/00 alliance semiconductor 9 ordering codes part numbering system speed (ns) ordering code package type operating range 55/70/100 AS6UA25617-bc 48-ball fine pitch bga commercial AS6UA25617-tc 44-pin tsop ii AS6UA25617-bi 48-ball fine pitch bga industrial a6ua25617-ti 44-pin tsop ii as6ua 25617 b, t c, i sram intelliwatt? prefix device number package: b: csp bga t: tsop ii temperature range: c: commercial: 0 c to 70 c i: industrial: -40 c to 85 c
|
